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Question on schematic


kalashnikov.alexande 2020/12/13 15:33

Hello.

I have checked v2_2 schematics[1] and found several places that I am unable to understand.
For example:  R3 and R1, or R4 and R2. Seems like U1 and U2 have different current limits on VDD because of that. And RFSW−REF signal comes through two resistors to U1 and through only one to U2.
Is that intended?

Most of the inductances have only "fb" or "rffb" instead of their nominal. For example: L603 and L604.

R607-609 + C620-622 are RC filters for SPI signals for U601. But there are no any for similar adf4350(U401).

And more I am looking into schematics, more I see weird things.

Is that schematics is up to date at all, or maybe I am just missing something?
Could, please, someone help me to understand at least some of that things?

Thank you!

[1] https://raw.githubusercontent.com/nanovna/NanoVNA-V2/master/v2_2.pdf

Siegfried Jackstien 2020/12/14 14:24

Fb mean ferrite bead... And yes it is an inductance

Dg9bfc sigi



Am 14.12.2020 00:33 schrieb kalashnikov.alexander.b@gmail.com:

> Hello.
>
> I have checked v2_2 schematics[1] and found several places that I am unable
to understand.
> For example: R3 and R1, or R4 and R2. Seems like U1 and U2 have different
current limits on VDD because of that. And RFSW−REF signal comes through two
resistors to U1 and through only one to U2.
> Is that intended?
>
> Most of the inductances have only "fb" or "rffb" instead of their nominal.
For example: L603 and L604.
>
> R607-609 + C620-622 are RC filters for SPI signals for U601. But there are
no any for similar adf4350(U401).
>
> And more I am looking into schematics, more I see weird things.
>
> Is that schematics is up to date at all, or maybe I am just missing
something?
> Could, please, someone help me to understand at least some of that things?
>
> Thank you!
>
> [1] https://raw.githubusercontent.com/nanovna/NanoVNA-V2/master/v2_2.pdf



_._,_._,_

* * *

kalashnikov.alexande 2020/12/14 07:02

Hello, Siegfried Jackstien.

Thank you for the clarification!

Since that I am not native english speaker - FB  was understood by me like Feed Back.

I know that SMD ferrite beds has inductance. :) Everything not dielectric with physical dimensions has it.

Anyway, could please, somebody shed some light on R1 and R3 and R4 and R2? Why are they there in series for U1 only?
It seemed for me like they must be connected to U1 and U1 only.

Thank you.

Siegfried Jackstien 2020/12/14 15:21

i am just shooting in the dark here but could it be that there is a
slight delay added with those two resistors??

that the one switch that has only one resistor is a tiny bit faster as
the one with two resistors in the signal line??

no idea if that is planned to be the case (to lower noise??) or why it
is made that way ... so to have a preceise answer you may ask the
developers of that v2 circuit

dg9bfc sigi


Am 14.12.2020 um 15:02 schrieb kalashnikov.alexander.b@gmail.com:

Carlos Cabezas 2020/12/14 18:55

Hello Alexander,

My guess is R1, R2, R3 and R4 improves isolation by low pass filtering
the supply and control signal between U1 and U2 switches. However R3 and
R4 placement is a bit weird, i think that's an error and they should be
in series with U2 VDD and V3 as R1 and R2 are to U1.

Right now, R3 and R4 are just adding some rejection to supply and
control signal noise, but not between switches. It can be an error, or
maybe not, who knows!

Regards,
Carlos Caezas


El 14/12/2020 a las 16:02, kalashnikov.alexander.b@gmail.com escribió:

Jim Lux 2020/12/14 12:42

On 12/13/20 3:33 PM, kalashnikov.alexander.b@gmail.com wrote:
> Hello.
>
> I have checked v2_2 schematics[1] and found several places that I am
> unable to understand.
> For example:  R3 and R1, or R4 and R2. Seems like U1 and U2 have
> different current limits on VDD because of that. And RFSW−REF signal
> comes through two resistors to U1 and through only one to U2.
> Is that intended?

I would assume it's for filtering - so that the leakage out through the
select port and Vdd  of U1 don't get into U2.

You'll note the two switches are essentially cascaded, so the idea is to
get more isolation when switched away from the input.


The switch only has 25-30 dB of isolation, so cascading two will give
you 50-60 dB.  You need that if you're getting a strong reflection on
the "sending" port, you're seeing the entire Tx power, and that would
combine with the desired signal on the "receiving" port on a S21
measurement.

The data sheet doesn't give a "control to signal" isolation or a "Vdd to
signal" isolation spec - that's typically something you'd measure in a
breadboard, and then deal with it accordingly.


They may be slow, big, and consume power, but relays are pretty good at
low loss, good match, and good isolation.



>
> Most of the inductances have only "fb" or "rffb" instead of their
> nominal. For example: L603 and L604.
>
> R607-609 + C620-622 are RC filters for SPI signals for U601. But there
> are no any for similar adf4350(U401).


The Tx synth also has more filtering on it's Vdd, as well. Maybe it was
a leakage path into the receiver.

kalashnikov.alexande 2020/12/14 13:56

Hello, Jim Lux!

Thank you for answers!

> I would assume it's for filtering - so that the leakage out through the select port and Vdd  of U1 don't get into U2.
> You'll note the two switches are essentially cascaded, so the idea is to get more isolation when switched away from the input.

But current schematic adds second resistor in VDD path only for U1:

Would not it be better as in the following example with the same result but for both switches:

> The Tx synth also has more filtering on it's Vdd, as well. Maybe it was a leakage path into the receiver.

Ok,even if this is true, then why there is no similar R+C for ADF4350−LE0 signal for U401 as it is for ADF4350−LE1 of U601?

I am just trying to understand if that schematic is not a draft at all.

Thank you.

Carlos Cabezas 2020/12/14 23:18

No, it is not a draft. I have checked V2 and V2 Plus 4 PCBs and they are
connected that way.

El lun., 14 dic. 2020 22:56, <kalashnikov.alexander.b@gmail.com> escribió:

Jim Lux 2020/12/14 14:32

On 12/14/20 1:56 PM, kalashnikov.alexander.b@gmail.com wrote:
> Hello, Jim Lux!
>
> Thank you for answers!
>
> > I would assume it's for filtering - so that the leakage out through
> the select port and Vdd  of U1 don't get into U2.
> > You'll note the two switches are essentially cascaded, so the idea
> is to get more isolation when switched away from the input.
>
> But current schematic adds second resistor in VDD path only for U1:
>
>
>
> Would not it be better as in the following example with the same
> result but for both switches:

Perhaps. But maybe the layout is easier, or it "just works".

When one does a design, there's lots of alternate designs that all work.

The cascaded Vdd filters provides better isolation from the chip to the
3.3V rail, which is probably a good thing.

kalashnikov.alexande 2020/12/14 14:47

Hello, Carlos Cabezas!

Thank you for checking this. Then this schematic is working at least.
I guess that no one except author can help me in my questions, unfortunately.

Especially on R607-609 + C620-622 low path filters. They will filter out everything higher than 6Mhz, I guess. So SPI bandwidth there will hit half of that limit ~3Mhz or less and 100Khz or less of frequency change rate.Which means that it is by design can not sweep faster than 100 points/sec. Just because of SPI bandwidth limit.

Thank you.

kalashnikov.alexande 2020/12/14 14:52

On Mon, Dec 14, 2020 at 02:47 PM, <kalashnikov.alexander.b@gmail.com> wrote:

>
> faster than 100 points/sec

Sorry, my mistake. 100k points/sec.
It is more than enough, because ADC is not so fast.

Clifford Heath 2020/12/14 14:54

One comment I haven't seen here is about the CPU noise on GPIO control lines. CPUs are noisy things, and though from a software point-of-view we think of them as being logic-0 or logic-1, in reality they bounce around with all kinds of noise that's coming from elsewhere in the CPU via its internal supply rails. This explains the extra RC filtering on the control lines to the cascaded switches. When the second switch is off, there is already good attenuation of any noise that was injected into the first switch, and hence not so much need to filter the control lines to the first switch. Presumably the same argument can be applied to the reason the Tx SPI is filtered but not the Rx generator.

Unrelated, a ferrite bead is not a pure inductance. At low frequencies, it's a very low resistance (the inductance is not noticed). At middle frequency it is an inductor, but at very high frequencies it becomes a resistor, perhaps 5 or 10 ohms is typical, due to the magnetic loss resistance. In this configuration it can be used to attenuate *and absorb* fast signals. As an inductor it doesn't absorb the signals, but resonates or reflects the signal. When a circuit shows an inductor, it's usually being used for its inductive behaviour but when a ferrite bead is shown, what matters most is its absorptive behaviour.

kalashnikov.alexande 2020/12/14 15:08

Hello, Clifford Heath!

Thank you for your answers!

> When the second switch is off, there is already good attenuation of any noise that was injected into the first switch, and hence not so much need to filter the control lines to the first switch.

But both switches are controlled by the same signal RFSW−REFL.

> Unrelated, a ferrite bead is not a pure inductance. At low frequencies, it's a very low resistance (the inductance is not noticed). At middle frequency it is an inductor, but at very high frequencies it becomes a resistor, perhaps 5 or 10 ohms is typical, due to the magnetic loss resistance. In this configuration it can be used to attenuate *and absorb* fast signals. As an inductor it doesn't absorb the signals, but resonates or reflects the signal. When a circuit shows an inductor, it's usually being used for its inductive behaviour but when a ferrite bead is shown, what matters most is its absorptive behaviour.

Thank you for this great clarification!

Clifford Heath 2020/12/15 15:38

>
> > When the second switch is off, there is already good attenuation of any
> noise that was injected into the first switch, and hence not so much need
> to filter the control lines to the first switch.
>
> But both switches are controlled by the same signal RFSW−REFL.
>
>

The first switch (adjacent to the bridge) has two RC filters for both VDD and RESW_REFL signal, but the second switch has only one filter for these. The goal appears to be to avoid injecting noise into the bridge when the switches are off (receiver is looking at PORT2). When the first switch is off, the REFL port is connected to ground via R12 (50 ohms). The RF2 port (to the 2nd switch) is isolated by 24dB, so that switch doesn't need extra filtering to avoid injecting noise into the bridge in this mode.

Apparently there is no such concern when the switches are on and the receiver is looking at the reflected signal. Also there is no extra filtering R (just a C) on the VDD and control signals for the PORT2 switches. I can't justify those decisions, but I presume that Gabriel did her homework on it. Personally I would have just added the extra RC everywhere.

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